TSB43AB23PDT

Product Summary

The Texas Instruments TSB43AB23PDT device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23PDT device provides three 1394 ports that have separate cable bias (TPBIAS). The TSB43AB23PDT device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements. The TSB43AB23PDT design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data. The TSB43AB23PDT device provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The TSB43AB23PDT device also provides multiple isochronous contexts, multiple cacheline burst transfers, and advanced internal arbitration.

Parametrics

TSB43AB23PDT absolute maximum ratings: (1)Supply voltage range: –0.2 V to 2.2 V; (2)Input voltage range for PCI, VI, PHY, and Miscellaneous: –0.5 to VDD + 0.5 V; (3)Output voltage range for PCI, VO, PHY, and Miscellaneous: –0.5 to VDD + 0.5 V; (4)Input clamp current, IIK (VI < 0 or VI > VDD): ±20 mA; (5)Output clamp current, IOK (VO < 0 or VO > VDD): ±20 mA; (6)Electrostatic discharge, HBM: 2 kV; (7)Continuous total power dissipation: See Dissipation Rating Table; (8)Operating free-air temperature, TA: 0℃ to 70℃; (9)Storage temperature range, Tstg: –65℃ to 150℃; (10)Lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds: 260℃.

Features

TSB43AB23PDT features: (1)Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1); (2)Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000; (3)Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394; (4)Compliant with Intel Mobile Power Guideline 2000; (5)Ultralow-power sleep mode; (6)Cable power presence monitoring; (7)Separate cable bias (TPBIAS) for each port; (8)Two general-purpose I/Os; (9)Isochronous receive dual-buffer mode; (10)PME support per 1394 Open Host Controller Interface Specification.

Diagrams