ISP1761BE

Product Summary

The ISP1761BE is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with the advanced Philips Slave Host Controller and the Philips ISP1582 Peripheral Controller. The ISP1761BE has three USB ports. Port 1 can be configured to function as a downstream port, an upstream port or an OTG port; ports 2 and 3 are always configured as downstream ports.

Parametrics

Absolute maximum ratings: (1)VCC(I/O), supply voltage: -0.5 to +4.6 V; (2)VCC(5V0), supply voltage: -0.5 to +5.6 V; (3)VCC(C_IN), supply voltage: 4.5 V max; (4)Ilu, latch-up current at VI < 0 or VI > VCC: 100 mA max; (5)Vesd, electrostatic discharge voltage at ILI < 1 uA: -4000 to +4000 V; (6)Tstg, storage temperature: -40 to +125 ℃.

Features

Features: (1)Compliant with Universal Serial Bus SpecificatioRev. 2.0; supporting data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); (2)Integrated TransactioTranslator (TT) for Original USB (full-speed and low-speed)peripheral support; (3)Three USB ports that support three operational modes:Mode 1: Port 1 is aOTG Controller port, and ports 2 and 3 are Host Controller ports; Mode 2: Ports 1, 2 and 3 are Host Controller ports; Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller ports; ; (4)Supports OTG Host NegotiatioProtocol (HNP) and SessioRequest Protocol (SRP); (5)Multitasking support with Virtual Segmentatiofeature (up to four banks); (6)High-speed memory controller (variable latency and SRAM external interface); (7)Directly addressable memory architecture; (8)Generic processor interface to most CPUs, such as: Hitachi SH-3 and SH-4, Philips XA, Intel StrongARM NEC and Toshiba MIPS, Motorola DragonBall and PowerPC Reduced InstructioSet Computer (RISC) processors; (9)Configurable 32-bit and 16-bit external memory data bus; (10)Supports Programmed I/O (PIO) and Direct Memory Access (DMA); (11)Slave DMA implementatiooCPU interface for reducing the host system CPU load.

Diagrams