SAA7118E

Product Summary

The SAA7118E is a video capture device for applications at the image port of VGA controllers. The SAA7118E is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC with succeeding decimation filters from 27 to 13.5 MHz data rate. The SAA7118E combines a Clock Generation Circuit(CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit. The applications of the SAA7118E are PC-video capture and editing, Personal video recorders (time shifting), Cable, terrestrial, and satellite set-top boxes, nternet terminals, Flat-panel monitors, DVD-recordable players, AV-ready hard-disk drivers, Digital televisions/scan conversion, Video surveillance/security, Video editing/post production, Video phones, Video projectors, Digital VCRs.

Parametrics

SAA7118E absolute maximum ratings: (1)digital supply voltage:-0.5V to +4.6V; (2)analog supply voltage:-0.5V to +4.6V; (3)input voltage at analog inputs:-0.5V to VDDA + 0.5V; (4)output voltage at analog output:-0.5V to VDDA + 0.5V; (5)input voltage at digital inputs and outputs:-0.5V to +5.5V; (6)output voltage at digital outputs outputs active:-0.5V to VDDD + 0.5V; (7)voltage difference between VSSAn and VSSDn:100mV; (8)storage temperature:-65℃ to +150℃; (9)ambient temperature:0℃ to 70℃; (10)electrostatic discharge voltage at all pins:-2000V to +2000V.

Features

SAA7118E features: (1)PAL delay line for correcting PAL phase errors; (2)Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals; (3)User programmable sharpness control; (4)Detection of copy-protected signals according to the macrovision standard, indicating level of protection; (5)Up to eight analog Y + C inputs, split as desired; (6)Up to four analog component inputs, with embedded or separate sync, split as desired; (7)Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs); (8)Automatic Clamp Control (ACC) for CVBS, Y and C(or VSB) and component signals; (9)Switchable white peak control; (10)Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz); (11)Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties; (12)RGB component inputs; (13)Y-PB-PR component inputs; (14)Fast blanking between CVBS and synchronous component inputs; (15)Digital RGB to Y-CB-CR matrix.

Diagrams